The present invention relates to an interconnect structure and methods of fabricating the same. More particularly, the present invention relates to an interconnect structure having enhanced electromigration reliability in which a composite metal (M)-metal oxide (MOx)/dielectric cap is employed.
Generally, semiconductor devices include a plurality of circuits that form an integrated circuit (IC) fabricated on a semiconductor substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires formation of multilevel or multilayered schemes, such as, for example, single or dual damascene wiring structures. The wiring structure typically includes copper, Cu, since Cu based interconnects provide higher speed signal transmission between large numbers of transistors on a complex semiconductor chip as compared with aluminum, Al, based interconnects.
Within a typical interconnect structure, metal vias run perpendicular to the semiconductor substrate and metal lines run parallel to the semiconductor substrate. Further enhancement of the signal speed and reduction of signals in adjacent metal lines are achieved in today's IC product chips by embedding the metal lines and metal vias (e.g., conductive features) in a dielectric material having a dielectric constant of less than 4.0.
In semiconductor interconnect structures, electromigration (EM) has been identified as one metal failure mechanism. Electromigration is the transport of material caused by the gradual movement of the ions in a conductor due to the momentum transfer between conducting electrons and diffusing metal atoms. The effect is important in applications where high direct current densities are used, such as in microelectronics and related structures. As the structure size decreases, the practical significance of EM increases.
EM is one of the worst reliability concerns for very large scale integrated (VLSI) circuits and manufacturing since the 1960's. The problem not only needs to be overcome during the process development period in order to qualify the process, but it also persists through the lifetime of the chip. Voids are created inside the metal conductors of an interconnect structure due to metal ion movement caused by the high density of current flow.
Although the fast diffusion path in metal interconnects varies depending on the overall integration scheme and materials used for chip fabrication, it has been observed that metal atoms, such as Cu atoms, transported along the metal/post planarized dielectric cap interface play an important role on the EM lifetime projection. The EM initial voids first nucleate at the metal/dielectric cap interface and then grow in the direction to the bottom of the interconnect, which eventually results in a circuit dead opening.
It has been demonstrated that by replacing the Cu/dielectric interface with a Cu/metal interface can enhance electromigration resistance by greater than 100×. Prior art metal caps are typically comprised of a Co-containing alloy such as, for example, CoWP, which is selectively deposited atop of the Cu conductor region of the interconnect structure by a plating process. Although metal caps can improve the electromigration resistance of the interconnect structure, prior art metal cap plating processes have some drawbacks associated therewith. For example, it is difficult to reduce the thickness of a Co-containing alloy to a sub-5 nm range by conventional wet plating processes. Thus, the thicker Co-containing alloy caps will have a significant resistance impact to Cu lines as the Cu line is reduced to sub-50 nm. Moreover, conventional wet plating processes that are typically used in forming Co-containing alloy caps may have a detrimental impact by absorption to high porosity (greater than 25% porosity) ultra low k porous SiCOH dielectric films that are being presently implemented in sub-32 nm interconnect structures. Furthermore, the selective plating of Co-containing alloy caps is not perfectly selective and some of the cap material may extend onto the dielectric surface creating shorts in the interconnect structure.
It is also worth mentioning that during a clean in dilute hydrofluoric acid, which is generally used to clean the surface of the interconnect dielectric material, corrosion of metal caps may occur. This is particularly observed when CoWP is used as the metal cap material.
Moreover, the current high rf power reducing plasmas that are also used to clean the Cu surface prior to dielectric deposition or Co-containing alloy plating will cause substantial damage to the underlying low k dielectric material surface and degrade both the electrical and mechanical properties.